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Masterpiece-of-Coldplay-Viva-la-Vida

September 16th, 2008 admin No comments

I used to rule the world
Seas would rise when I gave the word
Now in the morning I sleep alone
Sweep the streets I used to own

I used to roll the dice
Feel the fear in my enemies eyes
Listen as the crowd would sing:
“Now the old king is dead! Long live the king!”

One minute I held the key
Next the walls were closed on me
And I discovered that my castles stand
Upon pillars of salt, and pillars of sand

I hear Jerusalem bells are ringing
Roman Cavalry choirs are singing
Be my mirror my sword and shield
My missionaries in a foreign field
For some reason I can not explain
Once you know there was never, never an honest word
That was when I ruled the world
(Ohhh)

It was the wicked and wild wind
Blew down the doors to let me in.
Shattered windows and the sound of drums
People could not believe what I’d become
Revolutionaries Wait
For my head on a silver plate
Just a puppet on a lonely string
Oh who would ever want to be king?

I hear Jerusalem bells are ringing
Roman Cavalry choirs are singing
Be my mirror my sword and shield
My missionaries in a foreign field
For some reason I can not explain
I know Saint Peter won’t call my name
Never an honest word
And that was when I ruled the world
(Ohhhhh Ohhh Ohhh)

Hear Jerusalem bells are ringings
Roman Cavalry choirs are singing
Be my mirror my sword and shield
My missionaries in a foreign field
For some reason I can not explain
I know Saint Peter will call my name
Never an honest word
But that was when I ruled the world
Oooooh Oooooh Oooooh

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DSLWEB is now no.1 in google de

August 7th, 2008 admin No comments

很牛很强大….

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VHDL Structural Descriptions 1 building blocks

August 6th, 2008 admin No comments

http://www.gmvhdl.com/building.htm

To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block. For the remainder of the tutorial we will refer to a block as a design, even though a complete design may be a collection of many blocks interconnected.
Read more…

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